View AD5680-15_8023550.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

5 v 18 - bit nano dac ? in a sot - 23 data sheet ad5680 features single 18 - bit nano dac 18- bit monotonic 12- bit accuracy guaranteed tiny 8 - lead sot - 23 package power - on reset to zero scale/midscale 4.5 v to 5.5 v power supply serial interface rail - to - rail operation sync interrupt facility temp erature range: ?40c to +105c applications closed - loop process control low bandwidth data acquisition systems portable battery - powered instruments gain and offset adjustment precision setpoint control functional block dia gram v out v fb v dd gnd v ref ad5680 18-bit dac ref(+) power-on reset dac register input control logic din sclk sync 05854-001 output buffer figure 1. general description the ad5680 , a member of the nano dac family, is a single, 18- bit buffered voltage - out digital - to - analog converter (dac) that operates from a single 4.5 v to 5.5 v supply and is 18 - bit monotonic. the ad5680 requires an external reference voltage to set the output range of the dac. the part incorporates a power - on reset circuit that ensures the dac output p owers up to 0 v ( ad5680 - 1 ) or to midscale ( ad5680 - 2 ) and remains there until a valid write takes place. the low power consumption of th is part in normal operation makes it ideally suited to portable battery - operated equipment. the power consumption is 1.6 mw at 5 v. the ad5680 on - chip precision output amplifier allows rail - to - ra il output swing to be achieved. for remote sensing applications, the output amplifiers inverting input is available to the user. the ad5680 uses a versatile 3 - wire serial interface that operate s at clock rates up to 30 mhz, and is compatible with standard spi?, qspi?, microwire?, and dsp interface standards. product highlights 1. 18 bits of resolution. 2. 12- bit accuracy guaranteed for 18 - bit dac. 3. available in an 8 - lead sot - 23. 4. low power; typically co nsumes 1.6 mw at 5 v. 5. power - on reset to zero scale or to midscale. related devices ad5662 16- bit dac in sot - 23. rev. b document feedback information furnished by analog devices is believed to be accurate and reliabl e. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implicatio n or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2006 C 2014 analog devices, inc. all rights reserved. technical support www.analog.com
ad5680 da ta sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 related devices ................................................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing characteristics ................................................................ 4 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 pin configurations and function descriptions ........................... 6 typical performance characteristics ............................................. 7 terminology .................................................................................... 10 theory of operation ...................................................................... 11 dac section ................................................................................ 11 resistor string ............................................................................. 11 output amplifier ........................................................................ 11 interpolator architecture .......................................................... 11 serial interface ............................................................................ 12 input shift register .................................................................... 12 sync interrupt .......................................................................... 12 power - on reset .......................................................................... 12 microprocessor interfacing ....................................................... 13 applications information .............................................................. 14 closed - loop applications ......................................................... 14 filter ............................................................................................. 14 choosing a reference for the ad5680 .................................... 15 using a reference as a power supply for the ad5680 .......... 16 using the ad5680 with a galvanically isolated interface .... 16 power supply bypassing and grounding ................................ 16 outline dimensions ....................................................................... 17 ordering guide .......................................................................... 17 revision history 2/14 rev. a to rev. b added 8 - lead lfcsp ......................................................... universal changes to figure 3 caption and table 4 caption ...................... 6 added figure 4; renumb ered sequentially .................................. 6 updated outline dimensions ....................................................... 17 changes to ordering guide .......................................................... 17 3/07 rev. 0 to rev. a changes to input shift register section ...................................... 12 changes to figure 25 ...................................................................... 12 6/06 revision 0: initial version rev. b | page 2 of 20
data sheet ad5680 specifications v dd = 4.5 v to 5.5 v; r l = 2 k? to gnd; c l = 200 pf to gnd; v ref = v dd ; all specifications t min to t max , unless otherwise noted. table 1 . b grade 1 parameter min typ max unit conditions/comments static performance 2 resolution 18 bits relativ e accuracy 32 64 lsb differential nonlinearity 3 1 lsb measured in 50 hz system bandwidth 2 lsb measured in 300 hz system bandwidth zero - code error 2 10 mv all 0s loaded to dac register full - scale error ?0.2 ?1 % fsr all 1s loaded to dac re gister offset error 10 mv gain error 1.5 % fsr zero - code error drift 2 v/c gain temperature coefficient 2.5 ppm of fsr/c dc power supply rejection ratio ?100 db dac code = midscale; v dd = 5 v 10% output characteristics 3 output voltage range 0 v dd v output voltage settling time 80 85 s ? to ? scale change settling to 8 lsb , r l = 2 k?; 0 pf < c l < 200 pf slew rate 1.5 v/s ? to ? scale capacitive load stability 2 nf r l = 10 nf r l = 2 k? output noise spectral density 4 80 nv/hz dac code = midscale, 10 khz output noise (0.1 hz to 10 hz) 4 25 v p -p dac code = midscale total harmonic distortion (thd) 4 ?80 db v ref = 2 v 300 mv p - p, f = 200 hz digital -to - analog glitch impulse 5 nv -s 1 lsb change around major carry digital feedthrough 0.2 nv -s dc output impedance 0.5 ? short - circuit current 4 30 ma v dd = 5 v reference input reference current 40 75 a v ref = v dd = 5 v reference input range 5 0.75 v dd v reference input impedance 125 k? logic i nputs 3 input current 2 a all digital inputs v inl , input low voltage 0.8 v v dd = 5 v v inh , input high voltage 2 v v dd = 5 v pin capacitance 3 pf power requirements v dd 4.5 5.5 v all digital inputs at 0 v or v dd i dd (normal mode) dac active and excluding load current v dd = 4.5 v to 5.5 v 325 450 a v ih = v dd and v il = gnd power efficiency i out /i dd 85 % i load = 2 ma, v dd = 5 v 1 temperature range for b version is ?40c to +10 5c, typical at +25c. 2 dc specifications tested with the outputs unloaded, unless otherwise stated. linearity calculated using a reduced code range o f 2048 to 260,096. 3 guaranteed by design and characterization ; not production tested. 4 output unloaded. 5 reference input range at ambient where maximum dnl specification is achievable. rev. b | page 3 of 20
ad5680 da ta sheet timing characteristi cs all input signals are specified with t r = t f = 1 ns/v (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. see figure 2 . v dd = 4.5 v to 5.5 v; all specifications t min to t max , unless otherwise noted. table 2 . limit at t min , t max parameter v dd = 4.5 v to 5.5 v unit conditions/comments t 1 1 33 ns min sclk cycle time t 2 13 ns min sclk high time t 3 13 ns min sclk low time t 4 13 ns min sync to sclk falling edge setup time t 5 5 ns min data setup time t 6 4.5 ns min data hold time t 7 0 ns min sclk falling edge to sync rising edge t 8 33 ns min minimum sync high time t 9 13 ns min sync rising edge to sclk fall ignore t 10 0 ns min sclk falling edge to sync fall ignore 1 maximum sclk frequency is 30 mhz at v dd = 4.5 v to 5.5 v . din sync sclk db23 db0 t 9 t 10 t 4 t 3 t 2 t 7 t 6 t 5 t 1 t 8 05854-002 figure 2 . serial write operation rev. b | page 4 of 20
data sheet ad5680 absolute maximum rat ings t a = 25c, unless otherwise noted. table 3 . parameter rating v dd to gnd ?0.3 v to +7 v v out to gnd ?0.3 v to v dd + 0.3 v v fb to gnd ?0.3 v to v dd + 0.3 v v ref to gnd ?0.3 v to v dd + 0.3 v digital input voltage to gnd ?0.3 v to v dd + 0.3 v operating temperature range industrial (b version) ?40c to +105c storage te mperature range ?65c to +150c junction temperature (t j max) 150c power dissipation (t j max ? t a )/ ja ja thermal impedance sot - 23 package (4- layer board) 119c/w reflow soldering peak temperature pb - free 260c stresses above those listed un der absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution rev. b | page 5 of 20
ad5680 data sheet rev. b | page 6 of 20 pin configurations and function descriptions v dd 1 v ref 2 v fb 3 v out 4 gnd 8 din 7 sclk 6 sync 5 ad5680 top view (not to scale) 05854-003 figure 3. 8-lead sot-23 pin configuration 1v dd 2v ref 3v fb 4 v out 8gnd 7din 6sclk 5 sync 05854-104 ad5680 top view (not to scale) figure 4. 8-lead lfcsp pin configuration table 4. 8-lead sot-23 and 8-lead lfscp pin function descriptions pin no. mnemonic description 1 v dd power supply input. the part can be operated from 4.5 v to 5.5 v. v dd should be decoupled to gnd. 2 v ref reference voltage input. 3 v fb feedback connection for the output amplifier. v fb should be connected to v out for normal operation. 4 v out analog output voltage from dac. the outp ut amplifier has rail-to-rail operation. 5 sync level-triggered control input (active low). this is the frame synchronization signal for the input data. when sync goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks. the dac is updated following the 24 th clock cycle unless sync is taken high before this edge, in which case the rising edge of sync acts as an interrupt and the write sequence is ignored by the dac. sync 6 sclk serial clock input. data is clocked into the input shift register on the falling ed ge of the serial clock input. data can be transferred at rates up to 30 mhz. 7 din serial data input. this device has a 24-bit shift register. da ta is clocked into the register on the falling edge of the serial clock input. 8 gnd ground. ground reference point for all circuitry on the part.
data sheet ad5680 typical performance characteristics code in l error (lsb) 40 16 24 32 0 8 ?24 ?40 ?32 ?8 ?16 0 40k 80k 120k 160k 200k 240k 05854-028 v dd = v ref = 5v t a = 25c figure 5 . typical inl plot code dn l error (lsb) 1.0 0.6 0.4 0.2 0.8 0 ?0.4 ?0.2 ?0.6 ?1.0 ?0.8 0 25k 50k 100k 75k 125k 150k 225k 200k 175k 250k 05854-029 v dd = v ref = 5v t a = 25c figure 6 . typical dnl plot in 50 hz system bandwidth system bandwidth (hz) 0 0 dnl (lsb) 50 300 >300 4 1 2 v dd = 4.5v to 5.5v t = ?40c to +105c 05854-042 figure 7 . dnl performance vs. system bandwidth temper a ture ( c) error (% fsr) 0 ?0.04 ?0.02 ?0.06 ?0.08 ?0.10 ?0.18 ?0.16 ?0.14 ?0.12 ?0.20 ?40 ?20 40 20 0 100 80 60 05854-044 v dd = 5v gain error full-scale error figure 8 . gain error and full- scale error vs. temperature temper a ture ( c) error (mv) 1.5 1.0 0.5 0 ?2.0 ?1.5 ?1.0 ?0.5 ?2.5 ?40 ?20 40 20 0 80 60 100 05854-043 offset error zero-scale error figure 9 . zero - scale error and offset error vs. temperature i (ma) error vo lt age (v) 0.20 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 ?5 ?4 ?3 ?2 ?1 0 1 2 4 3 5 05854-014 v dd = v ref = 5 v , 3v t a = 25c dac loaded with zero scale ? sinking current dac loaded with full scale ? sourcing current figure 10 . headroom at rails vs. source and sink current rev. b | page 7 of 20
ad5680 da ta sheet 450 0 code i dd (a) 05854-007 0 50 100 150 200 250 300 350 400 4000 8000 12000 16000 20000 24000 v dd = v ref = 5v t a = 25c figure 11 . supply current vs. code 350 0 t e m p e r a t ur e (c) i dd (a) 05854-006 50 100 150 200 250 300 ?40 ?20 0 20 40 60 80 100 v dd = v ref = 5v figure 12 . supply current vs. temperature 700 0 100 0 5 v logic (v) i dd (a) 05854-004 200 300 400 500 600 1 2 3 4 v dd = 5v t a = 25c figure 13 . supply current vs. logic input voltage 05854-015 ch1 2.00v ch3 1.00v ch2 2.00v m 20.0 s ch4 1.30v 3 sclk d in v out 1 2 : 1.52v : 64.8 s @ : 1.20v figure 14 . full - scale settling time, 5 v 05854-016 ch1 3.00v ch3 100mv ch2 3.00v m 100s ch1 2.40v 3 v dd 1 2 v ref v out v out c3 max 284mv v out c3 min ?52mv figure 15 . power - on reset to 0 v 05854-017 ch1 3.00v ch3 500mv ch2 3.00v m 100s ch1 2.40v 3 v dd 1 2 v ref v out v out c3 max 2.5v v out c3 min ?40mv figure 16 . power - on reset to midscale rev. b | page 8 of 20
data sheet ad5680 sample number amplitude 2.502500 2.502250 2.502000 2.501750 2.501500 2.501250 2.501000 2.500750 2.500500 2.500250 2.500000 2.499750 2.499500 2.499250 2.499000 2.498750 0 150 200 250 50 100 300 350 400 450 500 550 05854-005 v dd = v ref = 5v t a = 25c 13ns/sample number 1 lsb change around midscale (0x20000 t o 0x1ffff) glitch impulse = 2.723n v -s figure 17 . digital - to- analog glitch impulse (negative) samples 6.5ns amplitude 2.5010 2.4986 0 05854-020 2.4988 2.4990 2.4992 2.4994 2.4996 2.4998 2.5000 2.5002 2.5004 2.5006 2.5008 50 100 150 200 250 300 350 400 450 500 v dd = v ref = 5v t a = 25c dac loaded with midscale digi t a l feedthrough = 0.201nv figure 18 . digital feedthrough frequenc y (khz) (db) ?20 ?100 0 10 05854-018 ?30 ?40 ?50 ?60 ?70 ?80 ?90 1 2 3 4 5 6 7 8 9 v dd = 5v t a = 25c ful l scale loaded v ref = 2v 300mv p-p figure 19 . tota l harmonic distortion ca p aci t ance (nf) time (s) 16 14 12 10 8 6 4 0 1 2 3 4 5 6 7 9 8 10 05854-027 v ref = v dd t a = 25c v dd = 5v v dd = 3v figure 20 . settling time vs. capacitive load 05854-019 5s/div 5 v/div 1 v dd = v ref = 5v t a = 25c dac loaded with midscale v ref figure 21 . 0.1 hz to 10 hz output noise plot frequenc y (hz) noise (nv/ hz) 1000 0 100 1m 05854-013 1k 10k 100k 900 800 700 600 500 400 300 200 100 v dd = v ref = 5v t a = 25c midscale loaded figure 22 . noise spectral density rev. b | page 9 of 20
ad5680 da ta sheet terminology relativ e accuracy or integral nonlinearity (inl) for the dac, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. figure 5 shows a typical inl vs. code plot. differential nonlinearity (dnl) differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. figure 6 shows a typical dnl vs. code plot. zero - code error zero - code error is a measurement of the output error when zero code (0x00000) is loaded to the dac register. ideally, the output should be 0 v. the zero - code error is always positive in the ad5680 because the output of the dac cannot go below 0 v. it is due to a combination of the offset errors in the dac and the output amplifier. z ero - code error is expressed in mv. a plot of zero - code error vs. temperature can be seen in figure 9 . full - scale error full - scale error is a measurement of the output error when full - scale code (0x3ffff) is loaded to the dac regis ter. ideally, the output should be v dd ? 1 lsb. full - scale error is expressed in percent of full - scale range. gain error this is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from ideal , expressed as a percent of the full - scale range. zero - code error drift this is a measurement of the change in zero - code error with a change in temperature. it is expressed in v/c. gain temperature coefficient this is a measurement of the change in gain error wit h a change in temperature. it is expressed in (ppm of full - scale range)/c. offset error offset error is a measure of the difference between v out (actual) and v out (ideal) , expressed in mv in the linear region of the transfer function. offset error is mea sured on the ad5680 with code 2048 loaded in the dac register. it can be negative or positive. dc power supply rejection ratio (psrr) this indicates how the output of the dac is affected by chan ges in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full - scale output of the dac. it is measured in db. v ref is held at 2 v, and v dd is varied by 10%. output voltage settling time this is the amount of time it takes f or the output of a dac to settle to a specified level for a ? to ? full - scale input change and is measured from the 24 th falling edge of sclk. digital -to - analog glitch impulse digital - to - analog glitch impulse is injected into the analog output when the inp ut code in the dac register changes state. it is normally specified as the area of the glitch in nv - s, and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x1ffff to 0x20000). see figure 17. digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac, but is measured when the dac output is not updated. it is specified in nv - s and measured with a full - scal e code change on the data bus, that is, from all 0s to all 1s and vice versa. total harmonic distortion (thd) this is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac. th e thd is a measurement of the harmonics present on the dac output. it is measured in db. noise spectral density this is a measurement of the internally generated random noise. random noise is characterized as a spectral density (voltage per hz). it is me asured by loading the dac to midscale and measuring noise at the output. it is measured in nv/hz. figure 22 shows a plot of noise spectral density. rev. b | page 10 of 20
data sheet ad5680 rev. b | page 11 of 20 theory of operation dac section the ad5680 dac is fabricated on a cmos process. the architecture consists of a string dac followed by an output buffer amplifier. figure 23 shows a block diagram of the dac architecture. v dd r r v out gnd resistor string ref (+) ref (?) output amplifier 05854-030 v fb dac register figure 23. dac architecture because the input coding to the dac is straight binary, the ideal output voltage is given by ? ? ? ? ? ? ? ? ?? 262,144 d vv ref out where d is the decimal equivalent of the binary code that is loaded to the dac register. it can range from 0 to 262,143. resistor string the resistor string section is shown in figure 24. it is simply a string of resistors, each of value r. the code loaded to the dac register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaranteed monotonic. r r r r r to output amplifier 05854-031 figure 24. resistor string output amplifier the output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 v to v dd . this output buffer amplifier has a gain of 2 derived from a 50 k resistor divider network in the feedback path. the output amplifiers inverting input is available to the user, allowing for remote sensing. this v fb pin must be connected to v out for normal operation. it can drive a load of 2 k in parallel with 1000 pf to gnd. the source and sink capabilities of the output amplifier can be seen in figure 10. the slew rate is 1.5 v/s with a ? to ? full-scale settling time of 10 s. interpolator architecture the ad5680 contains a 16-bit dac with an internal clock generator and interpolator. the voltage levels generated by the 16-bit, 1 lsb step can be subdivided using the interpolator to increase the resolution to 18 bits. the 18-bit input code can be divided into two segments: 16-bit dac code (db19 to db4) and 2-bit interpolator code (db3 and db2). the input to the dac is switched between a 16-bit code (for example, code 1023) and a 16-bit code + 1 lsb (for example, code 1024). the 2-bit interpolator code deter- mines the duty cycle of the switching and hence the 18-bit code level. see table 5 for an example. table 5. 18-bit code 16-bit dac code 2-bit interpolator code duty cycle db19 to db2 db19 to db4 db3 db2 4092 1023 0 0 0 4093 1023 0 1 25% 4094 1023 1 0 50% 4095 1023 1 1 75% 4096 1024 0 0 0 the dac output voltage is given by the average value of the waveform switching between 16-bit code (c) and 16-bit code + 1 (c + 1). the output voltage is a function of the duty cycle of the switching. 05854-032 c 2 16 16 18 +1 c c c plant dac v out filter 18-bit input code mux c + 1 clk interpolator 75% duty cycle 50% duty cycle 25% duty cycle c + 1 c + 1 c + 1 figure 25. interpolation architecture
ad5680 da ta sheet serial interface the ad5680 has a 3 - wire serial interface ( sync , sclk, and din) that is comp atible with spi, qspi, and microwire interface standards as well as with most dsps. see figure 2 for a timing diagram of a typical write sequence. the write sequence begins by bringing the sync line low. data from the din line is clocked into the 24 - bit shift register on the falling edge of sclk. the serial clock frequency can be as high as 30 mhz, making the ad5680 compatible with high speed dsps. o n the 24 th falling clock edge, the last data bit is clocked in and the programmed function is executed, that is, a change in dac register contents occurs. at this stage, the sync line can be kept low or brought high. in either case, it must be brought high for a minimum of 33 ns before the next write sequence so that a falling edge of sync can initiate the next write sequence. because the sync buffer draws more current when v in = 2 v than it does when v in = 0.8 v, sync should be idled low between write sequences for even lower power operation. as mentioned previously , it must, however, be brought high again just before the next write sequence. input shift register th e input shift register is 24 bits wide (see figure 26 ). the first two bits are dont care bits . b it db21 and bit db20 are reserved bits and should be set to 0 . the next 18 bits are the data bits followed by two dont care bits. th ese are transferred to the dac register on the 24 th falling edge of sclk. sync interrupt in a normal write sequence, the sync line is kept low for at least 24 falling edges of sclk, and the dac is updated on th e 24 th falling edge. however, if sync is brought high before the 24 th falling edge, this acts as an interrupt to the write sequence. the shift register is reset and the write sequence is seen as invalid . neither an update of the dac register contents nor a change in the operating mode occurs (see figure 27). power - on reset the ad5680 family contains a power - on reset circuit that controls the output v oltage during power - up. the ad5680 - 1 dac output powers up to 0 v, and the ad5680 - 2 dac output powers up to midscale. the output remain s there until a valid write sequence is made to the dac. this is useful in applications where it is important to know the output state of the dac while it is in the process of powering up. 05854-033 x x reserved bits 0 0 x x d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 data bits db23 (msb) db0 (lsb) figure 26 . input register contents 05854-034 din db23 db23 db0 db0 in v alid write sequence: sync high before 24 th f alling edge v alid write sequence: output upd a tes on the 24 th f alling edge sync sclk figure 27 . sync interrupt facility rev. b | page 12 of 20
data sheet ad5680 microprocessor inter facing ad5680 to blackfin? a dsp - bf53x interface figure 28 shows a serial interface between the ad5680 and the blackfin adsp - bf53x micr oprocessor. the adsp - bf53x processor family incorporates two dual - channel synchronous serial ports, sport1 and sport0, for serial and multiprocessor communications. using sport0 to connect to the ad5680 , the setup for the interface is as follows. dt0pri drives the din pin of the ad5680 , while tsclk0 drives the sclk of the pa rt. the sync is driven from tfs0. ad5680* *additiona l pins omitted for clarit y . tfs0 d t opri tsclk0 sync din sclk 05854-035 adsp-bf53x* figure 28 . ad5680 to blackfin adsp - bf53x interface ad5680 to 68hc11/68l11 interface figure 29 shows a serial interface between the ad5680 and the 68hc11/68l11 micr ocontroller. sck of the 68hc11/68l11 drives the sclk of the ad5680 , while the mosi output drives the serial data line of the dac. the sync signal is derived from a port line (pc 7). the setup conditions for correct operation o f this interface are as follows: the 68hc11/68l11 is configured with its cpol bit as 0 and its cpha bit as 1. when data is being transmitted to the dac, the sync line is taken low (pc7). whe n the 68hc11/68l11 is configured this way, data appearing on the mosi output is valid on the falling edge of sck. serial data from the 68hc11/68l11 is transmitted in 8 - bit bytes with only eight falling clock edges occurring in the transmit cycle. data is t ransmitted msb first. to load data to the ad5680 , pc7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the dac; pc7 is taken high at the end of this procedure. ad5680* *additiona l pins omitted for clarit y . pc7 sck mosi sync sclk din 05854-036 68hc 1 1/68l 1 1* figure 29 . ad5680 to 68hc11/68l11 interface ad5680 to 80c51/80l51 interface figure 30 shows a serial interface between the ad5680 and the 80c51/80l51 microcontroller. the setup for the interface is as follows. txd of the 80c51/80l51 drives sclk of the ad5680 , while rxd drives the serial data line of the part. the sync signal is again derived from a bit - programmable pin on the port. in this case, port line p3.3 is used. when da ta is to be transmitted to the ad5680 , p3.3 is taken low. the 80c51/80l51 transmits data in 8 - bit bytes only; thus , only eight falling clock edges occur in the transmit cycle. to load data to the dac, p3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. p3.3 is taken high following the completion of this cycle. the 80c51/80l51 outputs the serial data in a format tha t has the lsb first. the ad5680 must receive data with the msb first. the 80c51/80l51 transmit routine should take this into account. 80c51/80l51* ad5680* *additiona l pins omitted for clarit y . p3.3 txd rxd sync sclk din 05854-037 figure 30 . ad5680 to 80c51/80l51 interface ad5680 to microwire interface figure 31 shows an interface between the ad5680 and any microwire - compatible device. serial data is shifted out on the falling edge of the serial clock and is clocked into the ad5680 on the rising edge o f the sk. microwire* ad5680* *additiona l pins omitted for clarit y . cs sk so sync sclk din 05854-038 figure 31 . ad5680 to microwire interface rev. b | page 13 of 20
ad5680 da ta sheet applications information closed - loop applications the ad5680 is suitable for closed - loop low bandwidth applica - tions. ideally, the system bandwidth acts as a filter on the dac output. (see the filter section for details of the dac output prefiltering and postfiltering.) the dac upd ates at the interpolation frequency of 10 khz. 05854-039 controller plant adc dac figure 32 . typical closed - loop application filter the dac output voltage for code transition 4092 to 4094 can be seen in figure 33 . this is the dac output unfiltered. code 4092 does not have any interpolation but c ode 4094 has inter polation with a 50% duty cycle (s ee table 5 ) . figure 34 shows the dac output with a 50 hz passive rc filter and figure 35 shows the output with a 300 hz passive rc filter. an rc combination of 320 k? and 10 nf has been used to achieve the 50 hz cutoff frequency, and an rc combination of 81 k? and 10 nf has been used to achieve the 300 hz cutoff frequency. 05854-024 ch1 20.0v m 500 s ch4 0v 1 code 4092 code 4094 figure 33 . dac output unfiltered 05854-025 1 code 4092 code 4094 : 2.09ms @ : 1.28ms ch1 20.0v ch2 5v m 500 s ch2 1.4v 2 figure 34 . dac output with 50 hz filter on output 05854-026 1 code 4092 code 4094 : 2.09ms @ : 1.28ms ch1 20.0v ch2 5v m 500 s ch2 1.4v 2 figure 35 . dac output with 300 hz filter on output rev. b | page 14 of 20
data sheet ad5680 choosing a reference for the ad5680 to achieve the optimum performa nce from the ad5680 , choose a precision voltage reference carefully. the ad5680 has only one reference input, v ref . the voltage on the reference input is used to supply the positive input to the dac. therefore, any error in the reference is reflected in the dac. when choosing a voltage reference for high accuracy applica - tions, the sources of error are initial accuracy, ppm drift, long - term drift, and output voltage noise. initial accuracy on the output voltage of the dac leads to a full - scale error in the dac. to minimize these errors, a reference with high initial accuracy is preferred. in addition , choosing a reference with an output trim adjustment, such as the adr425 , allows a system designer to trim out system errors by setting a reference voltage to a voltage other than the nominal. the trim adjustment can also be used at t emperature to trim out any error. long - term drift is a measurement of how much the reference drifts over time. a reference with a tight long - term drift speci - fication ensures that the overall solution remains relatively stable during its entire lifetime. the temperature coefficient of a references output voltage affects inl, dnl, and tue. a reference with a tight temperature coefficient specification should be chosen to reduce temperature dependence of the dac output voltage in ambient conditions. in hig h accuracy applications, which have a relatively low noise budget, reference output voltage noise needs to be considered. it is important to choose a reference with as low an output noise voltage as is practical for the system noise resolution required. pr ecision voltage references such as the adr425 produce low output noise in the 0.1 hz to 10 hz range. examples of recom - mended precision references for use as supply to the ad5680 are shown in the table 6 . table 6 . partial list of precision references for use with the ad5680 part no. initial a ccuracy (mv max) temperature drift (ppm / c max) 0.1 hz to 10 hz noise (v p - p typ) v out (v) adr425 2 3 3.4 5 adr395 6 25 5 5 ref195 2 5 50 5 rev. b | page 15 of 20
ad5680 da ta sheet using a reference as a power supply for the ad5680 because the supply current required by the ad5680 is extremely low, an alternative option is to use a voltage reference to supply the required voltage to the part (see figure 36 ). this is especially useful if the power supply is quite noisy, or if the system supply voltages are at some value other than 5 v, for example, 15 v. the voltage reference outputs a steady supply voltage for the ad5680 ; see table 6 for a suitable reference. if the low dropout ref195 is used, it m ust supply 325 a of current to the ad5680 , with no load on the output of the dac. when the dac output is loaded, the ref195 also needs to supply the current to the load. the total current required (with a 5 k? load on the dac output) is 325 a + (5 v/5 k?) = 1.33 ma the load regulation of the ref195 is typically 2 ppm/m a, which results in a 2.7 ppm (13.5 v) error for the 1.33 ma current drawn from it. this corresponds to a 0.177 lsb error. ad5680 sync sclk din 15v 5v v out = 0v t o 5v v ref v dd ref195 05854-040 250 a 3-wire serial interface figure 36 . ref195 as power supply to the ad5680 using the ad5680 with a galvanically isolated interface in process - control applications in industrial environments, it is often ne cessary to use a galvanically isolated interface to protect and isolate the contro lling circuitry from any hazardous common - mode voltages that might occur in the area where the dac is functioning. isocouplers provide isolation in excess of 3 kv. the ad5680 uses a 3 - wire serial logic interface, so the adum130x 3 - channel digital isolator provides the required isolation (see figure 37 ). the power supply to the part also needs to be isolated , which is done by using a transformer. on the dac side of the transformer, a 5 v regulator provides the 5 v supply required for the ad5680 . 0.1f 5v regul a t or gnd 05854-041 din sync sclk power 10f sdi sclk d at a ad5680 v out v ob v oa v oc v dd v ic v ib v ia adum130x figure 37 . ad5680 with a galvanically isolated interface power supply bypassi ng and grounding when accuracy is important in a circuit, it is helpful to carefully consider the p ower supply and ground return layout on the board . the printed circuit board containing the ad5680 should have separate analog and digital sections, each having its own area of the board. if the ad5680 is in a system where other devices require an agnd - to - dgnd connection, the connection should be made at one point only. this ground point should be as close as possible to the ad5680 . the power supply to the ad5680 should be bypassed with 10 f and 0.1 f capacitors. the capacitors should be located as close as possible to the device, with the 0.1 f capacitor ideally right up against the device. the 10 f capacitors should be the tanta - lum bead type. it is important that the 0.1 f capacitor has low effective series resistance (esr) and effective series inductance (esi), for example, common ceramic types of capacitors. this 0.1 f capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. the power supply line itself should have as large a trace as possible to provide a low impedance path and to reduce glitch effects on the supply line. clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. avoid crossover of digital and analog signals if p ossible. when traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects on the board. the best board layout tech - nique is the microstrip technique where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. however, this is not always possible with a 2 - layer board. rev. b | page 16 of 20
data sheet ad5680 outline dimensions compliant to jedec standards mo-178-ba 8 4 0 s e a t i n g p l a n e 1 . 9 5 b s c 0 . 6 5 b s c 0 . 6 0 b s c 7 6 1 2 3 4 5 3 . 0 0 2 . 9 0 2 . 8 0 3 . 0 0 2 . 8 0 2 . 6 0 1 . 7 0 1 . 6 0 1 . 5 0 1 . 3 0 1 . 1 5 0 . 9 0 0 . 1 5 m a x 0 . 0 5 m i n 1 . 4 5 m a x 0 . 9 5 m i n 0 . 2 2 m a x 0 . 0 8 m i n 0 . 3 8 m a x 0 . 2 2 m i n 0 . 6 0 0 . 4 5 0 . 3 0 pin 1 indicator 8 12-16- 2008-a figure 38 . 8 - lead small outline transistor package [sot - 23 ] (rj - 8) dimensions shown in millimeters t o p view 8 1 5 4 0.35 0.30 0.25 bottom view pin 1 index are a se a ting plane 0.80 0.75 0.70 0.203 ref 0.05 max 0.00 min 0.65 bsc 1.95 ref 3.10 3.00 sq 2.90 coplanarity 0.08 0.50 0.40 0.30 compliant to jedec standards mo-229-weec-2 02-23-20 1 1- a pin 1 corner c 0.130 45 figure 39 . 8 - lead lead frame chip scale package [lfcsp_wd] 3 mm 3 mm body, very very thin, dual lead (cp - 8 - 15) dimensions shown in millimeters ordering guide model 1 power - on reset to co de accuracy temperature range package description package option branding ad5680brjz - 1500rl7 zero 64 lsb inl ? 40c to +105c 8 -l ead sot - 23 rj -8 d3c ad5680brjz - 1reel7 zero 64 lsb inl ? 40c to +105c 8 -l ead sot - 23 rj -8 d3c ad5680brjz - 2500rl7 midscale 64 lsb inl ? 40c to +105c 8 -l ead sot - 23 rj -8 d3d ad5680brjz - 2reel7 midscale 64 lsb inl ? 40c to +105 c 8 -l ead sot - 23 rj -8 d3d ad5680 bcpz - 1 500 rl7 zero 64 lsb inl ? 40c to +105c 8 - lead lfcsp cp - 8 - 15 dln ad5680 bcpz - 1rl7 zero 64 lsb inl ? 40c to +105c 8 - lead lfcsp cp -8 -15 dln ad5680 bcpz - 2500rl7 midscale 64 lsb inl ? 40c to +105c 8 - lead lfcsp c p -8 -15 dlp ad5680 bcpz - 2rl7 midscale 64 lsb inl ? 40c to +105c 8 - lead lfcsp cp -8 -15 dlp 1 z = rohs compliant part. rev. b | page 17 of 20
ad5680 data sheet notes rev. b | page 18 of 20
data sheet ad5680 notes rev. b | page 19 of 20
ad5680 data sheet notes ? 2006 C 2014 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05854 - 0- 2/14(b) rev. b | page 20 of 20

▲Up To Search▲

Price & Availability of AD5680-15

	To Download AD5680-15 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .